1. Field of the Invention
The present invention relates to a semiconductor memory device and more specifically to a multi-bank system semiconductor memory device.
2. Description of the Background Art
As recent approaches to achieve higher speed of dynamic random access memories (DRAMs), the method of improving the transfer rate of data by accessing the data at a high frequency and the method of improving latency are used.
Since access to row circuitry is especially several times as slow as access to column circuitry in the DRAMs, considerable latency is required when the row circuitry is not activated. In recent years, therefore, the row circuitry has been divided into several banks to increase hit ratio at a row-related activated bank. Thus, such delay in latency as caused by the system has been eliminated and apparent performance of the DRAMs has been improved. The more the number of banks, the higher the performance in this case. However, several drawbacks are caused.
A conventional multi-bank system semiconductor memory device 9000 will be described in the following with reference to FIG. 11. FIG. 11 representatively shows an example where row circuitry is divided into sixteen banks. In the figure, reference numbers 5, 6 and 9 denote a 2-bit global data input/output line, a local data input/output line and a transmission line for transmitting a column bank control signal described below. Further, reference number 8 denotes part of a dividing region 15 described below.
Conventional semiconductor memory device 9000 includes a plurality of banks 10#0, 10#1, 10#2, . . . , 10#15 and a plurality of sense amplifier bands 20#0, 20#1, 20#2, . . . , 20#15, 20#16 and has the configuration of a shared sense amplifier type. The banks can operate independently from one another. The banks each include a plurality of memory cell arrays.
Conventional semiconductor memory device 9000 further includes, a column bank control circuit 100, a column-related control circuit 102, a row-related/row bank control circuit 104 and a row decoder 106.
Column-related control circuit 102 includes a column decoder, a write.read buffer and so on. A read signal from each memory cell array is transmitted from global data input/output line 5 to column-related control circuit 102 and processed.
The sense amplifier bands each include a plurality of sense amplifiers. A read signal from a memory cell is amplified by a sense amplifier and transmitted to local data input/output line 6 that is arranged in the word line direction (row direction).
A signal on local data input/output line 6 is transmitted to global data input/output line 5 that is arranged in the direction of a column selection line (column direction). Global data input/output line 5 is arranged commonly to the same column in a plurality of banks.
Which bank and global data input/output line 5 are connected together is controlled in accordance with a column-related active signal (more specifically, a column bank control signal). Column bank control circuit 100 supplies, in accordance with a column-related bank address, the column bank control signal to transmission line 9 that runs on a sense amplifier band.
Here, the relations between the sense amplifier band and the banks will be described in detail with reference to FIG. 12.
In FIG. 12, bank 10#0 and corresponding sense amplifier band 20#0 are shown as an example. Bank 10#0 includes a plurality of memory cell arrays 12 divided corresponding to a plurality of columns. Memory cell arrays 12 are separated from one another by sub decode bands (in the case of a divided word line configuration) or pile-driven word line regions 15 (in the case of a word line shunt method, the region is hereinafter referred to as dividing regions 15). Here, reference number 4 denotes a bit line pair.
A specific configuration of the sub decode band will be described with reference to FIG. 13. As shown in FIG. 13, the sub decode band (reference number 15 in the figure) includes a plurality of sub decode circuits 16#0, 16#1, 16#2, . . . , 16#i. The sub decode circuits are arranged corresponding to main word lines MWL#0, MWL#1, MWL#2, . . .
Sub decode circuit 16#0 will be representatively described. Sub decode circuit 16#0 includes AND circuits 17#0, 17#1, 17#2 and 17#3. AND circuits 17#2 and 17#3 output, in response to a signal on main word line MWL#0 and a signal on a sub decode line 18, sub decode signals SWL#10 and SWL#11 for one adjacent memory cell array 12.
AND circuits 17#0 and 17#1 output, in response to a signal on main word line MWL#0 and a signal on sub decode line 18, sub decode signals SWL#00 and SWL#01 for the other adjacent memory cell array 12, not shown.
Referring to FIG. 12, sense amplifier band 20#0 includes a sense amplifier 26, a data input/output-related switch circuit 22 and a sense amplifier-related switch circuit 24. Data input/output-related switch circuit 22 and sense amplifier-related switch circuit 24 are arranged in the row direction.
Data input/output-related switch circuit 22 is arranged at a crossing area of a series of dividing regions 15 in the column direction and a sense amplifier band. Data input/output-related switch circuit 22 directly controls connection of global data input/output line 5 and local data input/output line 6 in accordance with column bank control signal CBS received from transmission line 9. Thus, local data input/output line 6 connected to global data input/output line 5 is selected (a bank is selected).
In the multi-bank system, at least two banks may be activated simultaneously during a certain time period. In this case, column access for another bank may be performed while sense amplifier 26 amplifies the fine width of a signal. When column selection line 7 is activated at this time, data on another bank on the global data input/output line is transmitted to sense amplifier 26 and therefore memory cell data is destroyed.
Accordingly, sense amplifier-related switch circuit 24 is provided to directly control connection of sense amplifier 26 and local data input/output line 6 in accordance with column bank control signal CBS received from transmission line 9. Thus, sense amplifier 26 connected to local data input/output line 6 is selected.
A circuit configuration of data input/output-related switch circuit 22 will be described in the following with reference to FIG. 14. In FIG. 14, global data input/output line 5 is formed of global data input/output lines 5a and 5b, and local data input/output line 6 is formed of local data input/output lines 6a and 6b.
Data input/output-related switch circuit 22 includes gate circuits 23a and 23b and an inverter circuit 21. Inverter circuit 21 inverts column bank control signal CBS received from transmission line 9 and outputs a signal/CBS.
Gate circuit 23a is arranged corresponding to global data input/output line 5a and local data input/output line 6a. Gate circuit 23a transmits a signal on local data input/output line 6a to global data input/output line 5a in response to column bank control signal CBS and signal/CBS.
Gate circuit 23b is arranged corresponding to global data input/output line 5b and local data input/output line 6b. Gate circuit 23b transmits a signal on local data input/output line 6b to global data input/output line 5b in response to column bank control signal CBS and signal/CBS.
In this manner, local data input/output line 6 connected to global data input/output line 5 is selected by column bank control signal CBS corresponding to a bank.
A specific configuration of sense amplifier-related switch circuit 24 will be described in the following with reference to FIG. 15. FIG. 15 also shows the relations with sense amplifier 26.
Sense amplifier-related switch circuit 24 includes NMOS transistors N2a, N2b, N3a and N3b. NMOS transistors N3a and N3b constitute a column selection gate 25.
NMOS transistors N2a and N3a are connected in series between local data input/output line 6a and sense amplifier 26. NMOS transistors N2b and N3b are connected in series between local data input/output line 6b and sense amplifier 26.
NMOS transistors N2a and N2b have their gate electrodes connected to transmission line 9. NMOS transistors N3a and N3b have their gate electrodes connected to column selection line 7.
Column selection gate 25 is opened and closed in response to a signal on column selection line 7. NMOS transistors N2a and N2b are turned on/off in response to column bank control signal CBS received from transmission line 9.
Column selection line 7 selects memory cell array 12 in the column direction, and column bank control signal CBS selects sense amplifier 26 connected to local data input/output line 5.
However, the operation cycle of the column-related circuitry side is several times as fast as that of the row-related circuitry side. In the configuration of the above described conventional semiconductor memory device 9000, therefore, the column bank control signal CBS is transmitted from the row-related circuitry side and thus the timing of the row-related circuitry and column-related circuitry sides is difficult to match. Accordingly, the configuration is not suitable for a high speed operation.
Further, transmission line 9 for transmitting the column bank control signal CBS has a considerable load. In the case of a one-directional input (input in the row direction) from column bank control circuit 100, therefore, the speed of signal transmission is different between switch circuits (the sense amplifier-related switch circuit and the data input/output-related switch circuit) closest to the row decoder and switch circuits farthest from the row decoder. Thus, achievement of higher operating speed is hindered.